1. Field of the Invention
The present invention relates generally to microelectronic structures and fabrication methods, and more particularly to the formation of a low resistance gate electrode layer.
2. Background
Advances in semiconductor manufacturing technology have led to the development of integrated circuits having smaller and smaller dimensions. Transistor sizes are not the only elements of integrated circuits reaching these smaller dimensions with advancing generations of semiconductor manufacturing processes. In fact, interconnect lines have been shrinking as well, in both height and width.
Interconnect lines are electrically conductive pathways, and are referred to in the field variously as lines, traces, wires, conductors, signal paths and signaling media. These related terms, are generally interchangeable, and appear in order from specific to general. Metal lines, generally aluminum (Al), copper (Cu) or an alloy of Al and Cu, are conductors that provide signal paths for coupling, i.e., interconnecting, electrical circuitry.
However, conductors other than metal are available in microelectronic devices. Materials such as doped polysilicon, doped single-crystal silicon (often referred to simply as diffusion, regardless of whether such doping is achieved by thermal diffusion or ion implantation), titanium (Ti), molybdenum (Mo), and refractory metal silicides are examples of other conductors.
As the cross-sectional dimensions of the various interconnect lines shrink, there is a corresponding increase in the electrical resistance of these interconnect lines. This is particularly aggravating for polysilicon lines since the sheet resistance of polysilicon is substantially higher than that of the more commonly used metal interconnects.
Additionally, polysilicon lines are typically used to form the gate electrode of metal oxide semiconductor field effect transistors (MOSFETs). An increase in the electrical resistance of the polysilicon therefore tends to limit the gate width that can be used in high speed circuit designs, since the signal propagation delay resulting from the high resistance of the gate electrode will manifest itself as a transistor that is slow to turn on, and slow to turn off.
Layout techniques, such as segmentation of a MOSFET into several shorter legs to achieve a given electrical gate width while reducing propagation delay, have been used, but these have their own drawbacks such as consuming more chip area. Similarly, silicide layers have been formed on polysilicon gate electrodes but the resistance of even these multi-layer gate electrodes remains higher than desirable.
What is needed is a structure that provides low resistance gate electrodes, and methods of making such a structure.